Microprocessor Design & Organisation


Tentative Lecture Schedule (Refer to MIP for a more updated one)


Wk
Lecture
1
Introduction to Computer Architecture
2
Computer Performance and Cost
3
Machine Cycle, State Diagrams, Buses
4
Cache Memory
5
Cache Memory (cont.)
6
Internal Memory
7
External Memory
8
Input/Output
9
RAID
10
Hazards & Pipelining
11
Buffer
12
Buffer
13
Class Test - 50% Module Weight
14
Revision + Tutorial
15
Revision + Tutorial


Module Info

Code: HCA2102
Convenor: RHH
Coordinator: RHH
Prerequisite: None
Audience: BEE
Level: 2
Lectures: 3 Hrs/Wk
Practicals: None
Control Assignment: 40%
Exams: 60%

Module Information Pack

BEE21BFT (1.968 KB)